Some integrated circuits contain logic circuits and memory cells having n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors. To reduce fabrication costs, the NMOS transistors in the memory cells and the logic circuits may be formed concurrently using the same ion implant steps and photolithographic steps, and similarly for the PMOS transistors in the memory cells and the logic circuits. Forming the transistor in the memory cells and logic circuit using the same implant doses undesirably reduces speed in the logic circuits due to channel stop implants under source and drain junctions of the transistors increasing junction capacitances. Further, leakage current in the memory cells is undesirably increased due to limited doses in the channel stop implants. Increasing or decreasing the channel stop dose adversely impacts the logic speed or memory cell leakage current, respectively. Using dedicated implant operations for separate channel stops in the logic and memory cells requires additional photolithographic steps and hence undesirably increases fabrication costs.